#ChipScope Core Inserter Project File Version 3.0
#Thu Dec 03 11:45:09 CST 2015
Project.device.designInputFile=E\:\\Projects\\NaiveMIPS-HDL\\xilinx\\NaiveMIPS\\soc_toplevel_cs.ngc
Project.device.designOutputFile=E\:\\Projects\\NaiveMIPS-HDL\\xilinx\\NaiveMIPS\\soc_toplevel_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=E\:\\Projects\\NaiveMIPS-HDL\\xilinx\\NaiveMIPS\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=4
Project.filter<0>=
Project.filter<1>=uart0
Project.filter<2>=uart*
Project.filter<3>=uart
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=16384
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=8
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=uart0/rx1/data_available
Project.unit<0>.triggerChannel<0><1>=uart0/rx1/rx_available
Project.unit<0>.triggerChannel<0><2>=rxd_IBUF
Project.unit<0>.triggerChannel<0><3>=
Project.unit<0>.triggerChannel<0><4>=
Project.unit<0>.triggerChannel<0><5>=
Project.unit<0>.triggerChannel<0><6>=
Project.unit<0>.triggerChannel<0><7>=
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCount<2>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<2><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerMatchType<1><0>=1
Project.unit<0>.triggerMatchType<2><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
Project.unit<0>.triggerPortWidth<0>=3
Project.unit<0>.triggerPortWidth<1>=8
Project.unit<0>.triggerPortWidth<2>=8
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
